EDS1216AABH, EDS1216CABH
Relationship Between Frequency and Minimum Latency
Frequency (MHz)
tCK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to activecommand
(same bank)
Write recovery or data-in to precharge
command (same bank)
133
7.5
100
Symbol
10
2
Unit
tCK
Notes
1
lRCD
3
9
6
3
2
lRC
7
5
2
2
tCK
tCK
tCK
tCK
1
1
1
1
lRAS
lRP
lDPL
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
lRRD
lSREX
lDAL
2
1
5
2
1
4
tCK
tCK
tCK
1
2
= [lDPL + lRP]
= [lRC]
3
Self refresh exit to command input
lSEC
9
7
tCK
Precharge command to high impedance
(CL = 2)
(CL = 3)
Last data out to active command
(Auto precharge, same bank)
lHZP
lHZP
lAPR
—
3
2
3
1
tCK
tCK
tCK
1
Last data out to precharge (early
precharge)
(CL = 2)
lEP
—
–1
tCK
(CL = 3)
lEP
–2
1
–2
1
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Column command to column command
Write command to data in latency
DQM to data in
lCCD
lWCD
lDID
0
0
0
0
DQM to data out
lDOD
lCLE
lMRD
lCDD
lPEC
2
2
CKE to CLK disable
1
1
Register set to active command
/CS to command disable
Power down exit to command input
2
2
0
0
1
1
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Data Sheet E0410E40 (Ver. 4.0)
9
ELPIDA [ ELPIDA MEMORY ]
