EDS1216AABH, EDS1216CABH
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS1216AA]
(TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS1216CA]
EDS1216AA
max.
EDS1216CA
max.
Parameter
Symbol
IDD1
Grade
Unit
mA
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
Notes
1, 2, 3
Operating current
100
3
100
3
Standby current in power
down
Standby current in power
down (input signal stable)
Standby current in non power
down
Standby current in non power
down (input signal stable)
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
mA
mA
mA
mA
mA
6
2
2
CKE = VIL, tCK = ∞
7
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
20
9
20
9
4
8
Active standby current in
power down
4
4
1, 2, 6
Active standby current in
power down (input signal
stable)
Active standby current in non
power down
Active standby current in non
power down (input signal
stable)
IDD3PS
IDD3N
3
3
mA
mA
mA
CKE = VIL, tCK = ∞
2, 7
CKE, /CS = VIH,
tCK = tCK (min.)
40
25
40
25
1, 2, 4
2, 8
CKE = VIH, tCK = ∞,
/CS = VIH
IDD3NS
tCK = tCK (min.),
BL = 4
Burst operating current
Refresh current
IDD4
IDD5
IDD6
120
220
1.5
120
220
1.5
mA
mA
mA
1, 2, 5
3
tRC = tRC (min.)
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Self refresh current
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0410E40 (Ver. 4.0)
5
ELPIDA [ ELPIDA MEMORY ]
