EDS1216AABH, EDS1216CABH
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
R:b
C:a'
UDQM, LDQM
a
a+1 a+2 a+3
DQ (input)
DQ (output)
a
a+1 a+2 a+3
Bank 0
Active
Bank 0
Read
Bank 3
Active
Clock
suspend
Bank 0
Precharge
Bank 3
Precharge
Bank 0
Write
VIH
CKE
/CS
/RAS
/CAS
/WE
BS
R:a
C:a
R:b
C:a
a
Address
UDQM, LDQM
DQ (input)
a+1 a+2 a+3
DQ (output)
a
a+1
a+3
Bank 0
Active
Bank 0
Read
Bank 0
Write
Bank 0
Precharge
Bank 3
Active
Read/Burst write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
/CS
VIH
/RAS
/CAS
/WE
BS
Address
C:a
A10=1
R:a
UDQM
LDQM
DQ (input)
a
a+1
High-Z
DQ (output)
t
t
t
RC
RP
RC
Refresh cycle and
Read cycle
Active
Bank 0
Read
Bank 0
Auto Refresh
Precharge
If needed
Auto Refresh
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
Data Sheet E0410E40 (Ver. 4.0)
43
ELPIDA [ ELPIDA MEMORY ]
