EDS1216AABH, EDS1216CABH
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, UDQM and LDQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
CL=2
READ WRIT
UDQM
LDQM
CL=3
in B0
in B3
in B1 in B2
DQ (input)
BL = 4
Burst write
High-Z
DQ (output)
READ to WRITE Command Interval (1)
CLK
Command
READ
WRIT
UDQM
LDQM
2 clock
CL=2
out
out
out
out
out
in
in
in
in
in
in
in
in
DQ
CL=3
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, UDQM and LDQM must be set High so
that the output buffer becomes High-Z before data input.
Data Sheet E0410E40 (Ver. 4.0)
31
ELPIDA [ ELPIDA MEMORY ]
