EDJ1108BABG, EDJ1116BABG
DDR3 SDRAM Mode Register 0 [MR0]
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM.
It controls burst length, read burst type, /CAS latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various applications.
The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0 and BA1, while controlling the states of
address pins according to the table below.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address field
0*1
0
0
0*1 PPD
WR
DLL TM /CAS latency RBT CL
BL
Mode register 0
Burst length
A8
0
DLL reset
No
A7
0
Mode
Normal
Test
A3 Read burst type
A1
0
BL
8 (Fixed)
A0
0
0
1
Nibble sequential
Interleave
1
Yes
1
0
4 or 8 (on the fly)
4 (Fixed)
1
BA1 BA0
MRS mode
MR0
1
0
0
0
1
1
0
1
0
1
1
Reserved
1
Write recovery for autoprecharge
/CAS latency
MR1
A11 A10 A9
WR
A6
0
A5
0
A4
0
A2
Latency
MR2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
0
0
0
0
0
0
0
0
Reserved
MR3
2
5*
6*
7*
8*
0
0
1
5
2
2
2
0
1
0
6
A12 DLL Control for Precharge PD
0
1
1
7
0
1
Slow exit (DLL off)
Fast exit (DLL on)
1
0
0
8
2
10
12
*
1
0
1
9
10
2
*
1
1
0
Reserved
1
1
1
Reserved
Notes: 1. BA2 and A13 are reserved for future use and must be programmed to 0 during MRS.
2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.).
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer
(WR (min.) [cycles] = roundup tWR (ns) / tCK (ns)).
(The WR value in the mode register must be programmed to be equal or larger than WR (min.)
This is also used with tRP to determine tDAL.
MR0 Programming
Data Sheet E1248E40 (Ver. 4.0)
75
ELPIDA [ ELPIDA MEMORY ]
