EDJ1108BABG, EDJ1116BABG
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, /CK
VDD, VDDQ
/RESET
tCKSRX
max. (10 ns; 5tCK)
200 s
500 s
tIS
10ns
CKE
2
*
tDLLK
ZQcal
tXPR
tIS
tMRD
tMRD
MRS
MR3
tMRD
tMOD
tZQinit
Command
BA
1
MRS
MR2
MRS
MR1
MRS
MR0
*
tIS
ODT
DRAM_RTT
Notes: 1. From time point "Td" until "Tk", NOP or DESL commands must be
applied between MRS and ZQcal commands.
2. tXPR = max. (tXS; 5tCK)
: VIH or VIL
Reset and Initialization Sequence at Power-On Ramping
Reset and Initialization with Stable Power
The following sequence is required for /RESET at no power interruption initialization.
1. Assert /RESET below 0.2 × VDD anytime when reset is needed (all other inputs may be undefined). /RESET
needs to be maintained for minimum 100ns. CKE is pulled low before /RESET being de-asserted (minimum time
10ns).
2. Follow Power-Up Initialization Sequence steps 2 to 12.
3. The reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, /CK
VDD, VDDQ
/RESET
tCKSRX
max. (10 ns; 5tCK)
100ns
500 s
tIS
10ns
CKE
2
*
tDLLK
ZQCL
tXPR
tIS
tMRD
tMRD
MRS
MR3
tMRD
tMOD
tZQinit
Command
BA
1
MRS
MR2
MRS
MR1
MRS
MR0
*
tIS
ODT
DRAM_RTT
Notes: 1. From time point "Td" until"Tk", NOP or DESL commands must be
applied between MRS and ZQCL commands.
2. tXPR = max. (tXS; 5tCK)
: VIH or VIL
Reset Procedure at Power Stable Condition
Data Sheet E1248E40 (Ver. 4.0)
73
ELPIDA [ ELPIDA MEMORY ]
