EDJ1108BABG, EDJ1116BABG
Burst Length (MR0)
Read and write accesses to the DDR3 are burst oriented, with the burst length being programmable, as shown in the
figure MR0 Programming. The burst length determines the maximum number of column locations that can be
accessed for a given read or write command. Burst length options include fixed BC4, fixed BL8, and on the fly which
allows BC4 or BL8 to be selected coincident with the registration of a read on write command Via A12 (/BC).
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Burst Chop
In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than
for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of
burst length being selected on the fly via A12(/BC), the internal write operation starts at the same point in time like a
burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be
pulled in by two clocks.
Burst Type (MR0)
[Burst Length and Sequence]
Starting address
(A2, A1, A0)
Sequential addressing
(decimal)
Interleave addressing
(decimal)
Burst length
Operation
READ
4 (burst chop)
000
001
010
011
100
101
110
111
0VV
1VV
000
001
010
011
100
101
110
111
VVV
0, 1, 2, 3, T, T, T, T
1, 2, 3, 0, T, T, T, T
2, 3, 0, 1, T, T, T, T
3, 0, 1, 2, T, T, T, T
4, 5, 6, 7, T, T, T, T
5, 6, 7, 4, T, T, T, T
6, 7, 4, 5, T, T, T, T
7, 4, 5, 6, T, T, T, T
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, T, T, T, T
1, 0, 3, 2, T, T, T, T
2, 3, 0, 1, T, T, T, T
3, 2, 1, 0, T, T, T, T
4, 5, 6, 7, T, T, T, T
5, 4, 7, 6, T, T, T, T
6, 7, 4, 5, T, T, T, T
7, 6, 5, 4, T, T, T, T
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
WRITE
READ
8
WRITE
Remark: T: Output driver for data and strobes are in high impedance.
V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
X: Don’t Care.
Notes: 1. Page length is a function of I/O organization and column addressing
2. 0...7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.
Data Sheet E1248E40 (Ver. 4.0)
79
ELPIDA [ ELPIDA MEMORY ]
