EDJ1108BABG, EDJ1116BABG
CKE Truth Table
CKE
Previous
Current
Command (n)*3
/CS, /RAS, /CAS, /WE Operation (n)*3
Current state*2
Power-down
cycle (n-1)*1 cycle (n)*1
Notes
L
L
H
L
H
L
L
L
L
L
L
L
×
Maintain power-down
14, 15
L
DESL or NOP
×
Power-down exit
11, 14
Self-refresh
L
Maintain self-refresh
Self-refresh exit
15, 16
L
DESL or NOP
DESL or NOP
DESL or NOP
DESL or NOP
DESL or NOP
DESL or NOP
DESL or NOP
REFRESH
8, 12, 16
11, 13, 14
Bank Active
Reading
H
H
H
H
H
H
H
Active power-down entry
Power-down entry
11, 13, 14, 17
11, 13, 14, 17
Writing
Power-down entry
11, 13, 14, 17
Precharging
Refreshing
All banks idle
Power-down entry
Precharge power-down entry
Precharge power-down entry
Self-refresh entry
11
11, 13, 14, 18
9, 13, 18
Any state other than
listed above
H
H
Refer to the Command Truth Table
10
Remark: H = VIH. L = VIL. × = Don’t care
Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n−1) is the state of CKE at the previous clock
edge.
2. Current state is the state of the DDR3 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n).
ODT is not included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this
document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh.
6. CKE must be registered with the same value on tCKE (min.) consecutive positive clock edges. CKE must
remain at the valid input level the entire time it takes to achieve the tCKE (min.) clocks of registration.
Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS +
tCKE (min.) + tIH.
7. DESL and NOP are defined in the Command Truth Table.
8. On self-refresh exit, DESL or NOP commands must be issued on every clock edge occurring during the
tXS period. Read or ODT command may be issued only after tXSDLL is satisfied.
9. Self-refresh mode can only be entered from the all banks idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for power-down entry and exit are NOP and DESL only.
12. Valid commands for self-refresh exit are NOP and DESL only.
13. Self-refresh can not be entered while read or write operations, (extended) mode register set operations or
precharge operations are in progress. See section Power-Down and self-refresh Command for a detailed
list of restrictions.
14. The power-down does not perform any refresh operations.
15. “×” means “don’t care” (including floating around VREF) in self-refresh and power-down. It also applies to
address pins.
16. VREF (Both VREFDQ and VREFCA) must be maintained during self-refresh operation.
17. If all banks are closed at the conclusion of the read, write or precharge command, the precharge power-
down is entered, otherwise active power-down is entered.
18. Idle state means that all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress. CKE
is high and all timings from previous operation are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS,
etc.) as well as all self-refresh exit and power-down exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
Data Sheet E1248E40 (Ver. 4.0)
70
ELPIDA [ ELPIDA MEMORY ]
