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EDJ1108BABG-DG-E 参数 Datasheet PDF下载

EDJ1108BABG-DG-E图片预览
型号: EDJ1108BABG-DG-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 148 页 / 1878 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第53页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第54页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第55页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第56页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第58页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第59页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第60页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第61页  
EDJ1108BABG, EDJ1116BABG  
ODT AC Electrical Characteristics [DDR3-1066, 800]  
-AC, -AE, -AG  
-8A, -8C  
800  
Data rate (Mbps)  
Parameter  
1066  
min.  
Symbol  
tAON  
max.  
300  
min.  
max.  
400  
Unit  
ps  
Notes  
RTT turn-on  
–300  
–400  
7, 12, 37  
Asynchronous RTT turn-on delay  
tAONPD  
tAOF  
2
8.5  
2
8.5  
ns  
(power-down with DLL frozen)  
RTT_Nom and RTT_WR turn-off  
time from ODTLoff reference  
ODT turn-off (power-down mode) tAOFPD  
0.3  
0.7  
8.5  
0.3  
0.7  
8.5  
tCK (avg) 8, 12, 37  
2
2
ns  
ODT to power-down entry/exit  
latency  
tANPD  
WL – 1.0  
WL – 1.0  
nCK  
ODT turn-on Latency  
ODT turn-off Latency  
ODTLon  
ODTLoff  
WL – 2.0  
WL – 2.0  
WL – 2.0  
WL – 2.0  
WL – 2.0  
WL – 2.0  
WL – 2.0  
WL – 2.0  
nCK  
nCK  
ODT Latency for changing from  
RTT_Nom to RTT_WR  
ODTLcnw  
WL – 2.0  
WL – 2.0  
WL – 2.0  
WL – 2.0  
nCK  
ODT Latency for change from  
RTT_WR to RTT_Nom  
(BC4)  
ODTLcwn4  
4 + ODTLoff  
4 + ODTLoff  
nCK  
ODT Latency for change from  
RTT_WR to RTT_Nom  
(BL8)  
ODTLcwn8  
6 + ODTLoff  
6 + ODTLoff  
nCK  
ODT high time without WRIT  
command or with WRIT command ODTH4  
4
6
4
6
nCK  
nCK  
and BC4  
ODT high time with WRIT  
ODTH8  
command and BL8  
RTT dynamic change skew  
tADC  
0.3  
0.7  
0.3  
0.7  
tCK (avg) 12, 37  
nCK  
Power-up and reset calibration time tZQinit  
512  
512  
Normal operation full calibration  
tZQoper  
tZQCS  
256  
64  
256  
64  
nCK  
time  
Normal operation short calibration  
time  
nCK  
30  
Write Leveling Characteristics [DDR3-1066, 800]  
-AC, -AE, -AG  
-8A, -8C  
800  
1066  
min.  
Parameter  
Symbol  
max.  
min.  
max.  
Unit  
Notes  
3
First DQS pulse rising edge after  
write leveling mode is  
programmed  
DQS, /DQS delay after write  
leveling mode is programmed  
Write leveling setup time from  
rising CK, /CK crossing to rising tWLS  
DQS, /DQS crossing  
tWLMRD  
40  
40  
nCK  
nCK  
ps  
tWLDQSEN  
25  
25  
3
245  
325  
Write leveling hold time from  
rising DQS, /DQS crossing to  
rising CK, /CK crossing  
tWLH  
245  
325  
ps  
Write leveling output delay  
tWLO  
0
0
9
2
0
0
9
2
ns  
ns  
Write leveling output error  
tWLOE  
Data Sheet E1248E40 (Ver. 4.0)  
57  
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