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EDJ1108BABG-DG-E 参数 Datasheet PDF下载

EDJ1108BABG-DG-E图片预览
型号: EDJ1108BABG-DG-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 148 页 / 1878 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第49页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第50页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第51页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第52页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第54页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第55页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第56页浏览型号EDJ1108BABG-DG-E的Datasheet PDF文件第57页  
EDJ1108BABG, EDJ1116BABG  
ODT AC Electrical Characteristics [DDR3-1600, 1333]  
-GL, -GN  
-DG, -DJ  
1333  
Data rate (Mbps)  
Parameter  
1600  
min.  
Symbol  
tAON  
max.  
225  
min.  
max.  
250  
Unit  
ps  
Notes  
7, 12,  
37  
RTT turn-on  
225  
250  
Asynchronous RTT turn-on delay  
(power-down with DLL frozen)  
RTT_Nom and RTT_WR turn-off  
time from ODTLoff reference  
Asynchronous RTT turn-off delay  
(power-down with DLL frozen)  
ODT to power-down entry/exit  
latency  
tAONPD  
tAOF  
2
8.5  
0.7  
8.5  
2
8.5  
0.7  
8.5  
ns  
tCK  
(avg)  
8, 12,  
37  
0.3  
0.3  
tAOFPD  
tANPD  
2
2
ns  
WL – 1.0  
WL – 1.0  
nCK  
ODT turn-on Latency  
ODT turn-off Latency  
ODTLon  
ODTLoff  
WL – 2  
WL – 2  
WL – 2  
WL – 2  
WL – 2.0  
WL – 2.0  
WL – 2.0  
WL – 2.0  
nCK  
nCK  
ODT Latency for changing from  
RTT_Nom to RTT_WR  
ODT Latency for change from  
RTT_WR to RTT_Nom  
(BC4)  
ODTLcnw WL – 2  
ODTLcwn4  
WL – 2  
WL – 2.0  
WL – 2.0  
nCK  
nCK  
4 + ODTLoff  
4 + ODTLoff  
ODT Latency for change from  
RTT_WR to RTT_Nom  
(BL8)  
ODTLcwn8  
6 + ODTLoff  
6 + ODTLoff  
nCK  
ODT high time without WRIT  
command or with WRIT command ODTH4  
and BC4  
4
6
4
6
nCK  
nCK  
ODT high time with WRIT command  
ODTH8  
and BL8  
tCK  
RTT dynamic change skew  
tADC  
0.3  
0.7  
0.3  
0.7  
12, 37  
30  
(avg)  
Power-up and reset calibration time tZQinit  
Normal operation full calibration  
time  
Normal operation short calibration  
time  
512  
256  
512  
256  
nCK  
tZQoper  
tZQCS  
nCK  
64  
64  
nCK  
Write Leveling Characteristics [DDR3-1600, 1333]  
-GL, -GN  
-DG, -DJ  
1333  
1600  
Parameter  
Symbol  
min.  
max.  
min.  
max.  
Unit  
Notes  
First DQS pulse rising edge after  
write leveling mode is  
programmed  
DQS, /DQS delay after write  
leveling mode is programmed  
Write leveling setup time from  
rising CK, /CK crossing to rising tWLS  
DQS, /DQS crossing  
tWLMRD  
40  
40  
nCK  
nCK  
ps  
3
3
tWLDQSEN  
25  
25  
165  
195  
Write leveling hold time from  
rising DQS, /DQS crossing to  
rising CK, /CK crossing  
tWLH  
165  
195  
ps  
Write leveling output delay  
tWLO  
0
0
7.5  
2
0
0
9
2
ns  
ns  
Write leveling output error  
tWLOE  
Data Sheet E1248E40 (Ver. 4.0)  
53  
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