EDJ1108BABG, EDJ1116BABG
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V)
• New units tCK(avg) and nCK, are introduced in DDR3.
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
AC Characteristics [DDR3-1600, 1333]
-GL, -GN
-DG, -DJ
1333
Data rate (Mbps)
Parameter
1600
min.
Symbol
max.
3333
min.
max.
3333
Unit
ps
Notes
6
Average clock cycle time
Minimum clock cycle time
(DLL-off mode)
tCK (avg)
1250
1500
tCK (DLL-off) 8
8
ns
Average CK high-level width
tCH (avg)
tCL (avg)
0.47
0.53
0.53
0.47
0.47
0.53
0.53
tCK (avg)
tCK (avg)
Average CK low-level width
0.47
12.5 (GL)
12 (DG)
Active to read or write command delay tRCD
ns
ns
ns
26
26
13.75 (GN)
13.5 (DJ)
12.5 (GL)
13.75 (GN)
47.5 (GL)
48.75 (GN)
12 (DG)
13.5 (DJ)
48 (DG)
49.5 (DJ)
Precharge command period
tRP
Active to active/auto-refresh command
time
tRC
26
Active to precharge command
tRAS
35
9 × tREFI 36
9 × tREFI ns
26
Active bank A to active bank B
command period
(x8)
Active bank A to active bank B
command period
(x16)
Four active window
(x8)
(x16)
Address and control input hold time
(VIH/VIL (DC) levels)
Address and control input setup time
(VIH/VIL (AC) levels)
Address and control input setup time
(VIH/VIL (AC150) levels)
DQ and DM input hold time
(VIH/VIL (DC) levels)
DQ and DM input setup time
(VIH/VIL (AC) levels)
tRRD
tRRD
tRRD
tRRD
tFAW
tFAW
tIH (base)
6
6
ns
26, 27
26, 27
26, 27
26, 27
26
4
4
nCK
7.5
4
ns
nCK
ns
30
30
45
140
ns
26
120
45
ps
16, 23
tIS (base)
65
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
16, 23
tIS (base)
AC150
16, 23,
31
45 + 125
45
65 + 125
tDH (base)
tDS (base)
tIPW
65
17, 25
17, 25
32
10
30
Control and Address input pulse width
for each input
DQ and DM input pulse width for each
input
560
360
620
400
tDIPW
32
12, 13,
14, 37
12, 13,
14, 37
12, 13,
14, 37
12, 13,
14, 37
DQ high-impedance time
DQ low-impedance time
tHZ (DQ)
tLZ (DQ)
tHZ (DQS)
tLZ (DQS)
225
225
225
225
100
250
250
250
250
125
−450
−500
DQS, /DQS high-impedance time
(RL + BL/2 reference)
DQS, /DQS low-impedance time
(RL − 1 reference)
DQS, /DQS to DQ skew, per group, per
access
/CAS to /CAS command delay
Data Sheet E1248E40 (Ver. 4.0)
−450
−500
tDQSQ
tCCD
ps
12, 13
4
4
nCK
50
ELPIDA [ ELPIDA MEMORY ]
