EDJ1108BABG, EDJ1116BABG
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Tn Tn+1 Tn+2
CK
/CK
Command*3
Address*4
WRIT
PRE
NOP
tWR*5
Bank
Col n
tWPRE
tWPST
DQS, /DQS
DQ*2
Din
n
Din Din Din
n+1 n+2 n+3
WL = 5
VIH or VIL
Notes: 1. BC4, WL = 5, RL = 5.
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0.
5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7.
tWR specifies the last burst write cycle until the precharge command can be issued to the same bank .
Write to Precharge Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
CK
/CK
Command*3
Address*4
WRIT
NOP
WRIT
NOP
tCCD
tWR
tBL = 4 clocks
tWTR
Bank
Col n
Bank
Col b
tWPRE
tWPST
DQS, /DQS
DQ*2
Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b
b+1 b+2 b+3 b+4 b+5 b+6 b+7
WL = 5
WL = 5
Notes: 1. BL8, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
VIH or VIL
4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0 and T4.
WRITE (BL8) to WRITE (BL8)
Data Sheet E1248E40 (Ver. 4.0)
112
ELPIDA [ ELPIDA MEMORY ]
