EDJ1108BABG, EDJ1116BABG
Write Operation
During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (auto precharge can be enabled or disabled).
• A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
• A12 = 1, BL8
A12 will be used only for burst length control, not a column address.
The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of
the clock. The address inputs determine the starting column address. Write latency (WL) is equal to (AL + CWL). A
data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst
cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS
specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the
DQS until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ
pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the
completion of the burst write to bank precharge is the write recovery time (tWR).
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11 T12
T13
CK
/CK
Command*3
Address*4
NOP
WRIT
WL = AL + CWL
Bank
Col n
tWPRE
tWPST
DQS, /DQS
DQ*2
Din Din Din Din Din Din Din Din
n+1 n+2 n+3 n+4 n+5 n+6 n+7
n
VIH or VIL
Notes: 1. BL8, WL = 5 (AL = 0, CWL = 5)
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0.
Burst Write Operation, WL = 5
Data Sheet E1248E40 (Ver. 4.0)
110
ELPIDA [ ELPIDA MEMORY ]
