EDJ1108BABG, EDJ1116BABG
IDD7 Timing Patterns
The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables.
tFAW tFAW tRRD tRRD
Speed bins
Bin
Organization (ns)
(tCK) (ns)
(tCK) Timing Patterns
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4
RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D
DDR3-800
all
×8
40
16
10
4
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
D D
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3
RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6
RA6 D D D D A7 RA7 D D D D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
D D
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D
D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D D A6
RA6 D D D A7 RA7 D D D D D D D D D D D D D
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D
D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D
A7 RA7 D D D D D D D
all
all
all
all
all
all
×16
50
20
10
4
DDR3-1066
DDR3-1333
DDR3-1600
×8
37.5
50
20
27
20
30
24
7.5
10
6
4
6
4
5
5
×16
×8
30
×16
×8
45
7.5
6
30
Remark: Ax = Active command for bank x.
RAx = Read with auto precharge command from bank x.
ex. RA0 = READA command from bank 0
Notes: 1. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) and tFAW (IDD) using
a burst length = 8.
2. Control and address bus inputs are STABLE during DESELECTs.
3. IOUT = 0mA.
Data Sheet E1248E40 (Ver. 4.0)
40
ELPIDA [ ELPIDA MEMORY ]
