EDJ1108BABG, EDJ1116BABG
Case 2:
For certain CKE intensive operations, for example, repeated "PD Exit - Refresh - PD Entry" sequence, the number of
clock cycles between PD Exit and PD Entry may be insufficient to keep the DLL updated. Therefore the following
conditions must be met in addition to tPD in order to maintain proper DRAM operation when Refresh commands is
issued in between PD Exit and PD Entry.
Power-down mode can be used in conjunction with Refresh command if the following conditions are met:
1. tXP must be satisfied before issuing the command
2. tXPDLL must be satisfied (referenced to registration of PD exit) before next power-down can be entered.
T0 T1
Tn Tn+1
tIH
Tx
Ty
CK
/CK
tIH
CKE
tIS
tCPDED
tIS
tXPDLL (min.)
tCKE (min.)
tPD
Command
NOP NOP NOP
NOP
NOP
tXP
REF NOP NOP NOP NOP NOP NOP NOP
Exit power-down
Enter power-down
Power-Down Entry/Exit Clarifications (2)
Case 3:
If an early PD Entry is issued after Refresh command, once PD Exit is issued, NOP or DESL with CKE high must be
issued until tRFC from the refresh command is satisfied. This means CKE cannot be de-asserted twice within tRFC
window.
T0
T1
Tn
Tn+1
Tx
Ty
CK
/CK
tIH
tIH
CKE
tIS
tIS
tPD
tXPDLL
tCPDED
REF NOP NOP
tCKE (min.)
Command
NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid
N
tRFC (min.)
Exit power-down
Enter power-down
Note: * Synchronous ODT Timing starts at the end of tXPDLL (min.)
Power-Down Entry/Exit Clarifications (3)
Data Sheet E1248E40 (Ver. 4.0)
128
ELPIDA [ ELPIDA MEMORY ]
