EDJ1108BABG, EDJ1116BABG
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down
definition, these modes are:
• Active mode
• Idle mode with CKE high
• Active power-down mode (regardless of MR0 bit A12)
• Precharge power-down mode if DLL is enabled during precharge power-down by MR0 bit A12.
In synchronous ODT mode, RTT will be turned on or off ODTLon clock cycles after ODT is sampled high by a rising
clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency
is tied to the write latency (WL) by: ODTLon = WL – 2; ODTLoff = WL – 2.
ODT Latency and Posted ODT
In Synchronous ODT mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the
ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency
(AL) relative to the external ODT signal.
ODTLon = CWL + AL − 2; ODTLoff = CWL + AL − 2. For details, refer to DDR3 SDRAM latency definitions.
[ODT Latency Table]
Parameter
Symbol
ODTLon
ODTLoff
Value
Unit
nCK
nCK
ODT turn-on Latency
ODT turn-off Latency
WL – 2 = CWL + AL – 2
WL – 2 = CWL + AL – 2
Synchronous ODT Timing Parameters
In synchronous ODT mode, the following timing parameters apply (see Synchronous ODT Timing Examples (1)):
ODTLLow, ODTLLoff, tAON,(min.), (max.), tAOF,(min.),(max.) Minimum RTT turn-on time (tAON min) is the point in
time when the device leaves high impedance and ODT resistance begins to turn on. Maximum RTT turn-on time
(tAON max) is the point in time when the ODT resistance is fully on. Both are measured from ODTLon.
Minimum RTT turn-off time (tAOF min ) is the point in time when the device starts to turn-off the ODT resistance.
Maximum RTT turn-off time (tAOF max) is the point in time when the on-die termination has reached high
impedance. Both are measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the
SDRAM with ODT high, then ODT must remain high until ODTH4 (BL4) or ODTH8 (BL8) after the Write command
(see figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high
to ODT registered low or from the registration of a Write command until ODT is registered low.
Data Sheet E1248E40 (Ver. 4.0)
131
ELPIDA [ ELPIDA MEMORY ]
