EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
• DQS, /DQS crossing to Data Output
• tDQSQ; both rising/falling edges of DQS, no tAC defined
T0
T4
T5
T6
T7
T8
T9
T10
/CK
CK
Command*3
READ
NOP
RL = AL + CL
Bank
Coln
Address*4
tRPRE
tQH
tQH
tRPST
DQS, /DQS
tDQSQ(max.)
tDQSQ(max.)
tLZ(DQ)(max.)
tHZ(DQ)(max.)
Dout Dout
n+1
Dout Dout
n+2 n+3
Dout Dout Dout Dout
n+4 n+5 n+6 n+7
DQ*2
n
tLZ(DQ)(min.)
(Last data valid)
Dout Dout
n+1
Dout Dout
n+2 n+3
Dout Dout Dout Dout
n+4 n+5 n+6 n+7
DQ*2
n
(First data no longer valid)
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
All DQS collectively
Data valid
Data valid
VIH or VIL
Notes: 1. BL8, RL = 5(AL = 0, CL = 5).
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] and A12 = 1 during READ command at T0.
5. Output timings are referenced to VDDQ/2, and DLL on for locking.
6. tDQSQ defines the skew between DQS, /DQS to data and does not define DQS, /DQS to clock.
7. Early data transitions may not always happen at the same DQ.
Data transitions of a DQ can vary(either early or late) within a busy.
DDR3 Data Strobe to Data Relationship
Data Sheet E1375E50 (Ver. 5.0)
103
ELPIDA [ ELPIDA MEMORY ]
