EDE5104AGSE, EDE5108AGSE
max.
× 8
× 4
Parameter
Symbol Grade
Unit
mA
Test condition
tCK = tCK (IDD);
-6C
-6E
-5C
-4A
TBD
270
250
230
TBD
270
250
230
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Auto-refresh current IDD5
Self Refresh Mode;
CK and /CK at 0V;
Self-refresh current
IDD6
IDD7
6
6
mA
mA
CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD),
AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
-6C
-6E
-5C
-4A
TBD
300
300
280
TBD
320
320
300
Operating current
(Bank interleaving)
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS. IDD values must be met with all combinations
of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
DDR2-667
DDR2-533
4-4-4
4
DDR2-400
4-4-4
4
5-5-5
5
3-3-3
3
Parameter
CL(IDD)
Unit
tCK
ns
tRCD(IDD)
tRC(IDD)
12
15
15
15
57
60
60
55
ns
tRRD(IDD)
tCK(IDD)
7.5
3
7.5
3
7.5
7.5
5
ns
3.75
45
ns
tRAS(min.)(IDD)
tRAS(max.)(IDD)
tRP(IDD)
45
45
40
ns
70000
12
70000
15
70000
15
70000
15
ns
ns
tRFC(IDD)
105
105
105
105
ns
Preliminary Data Sheet E0715E20 (Ver. 2.0)
8
ELPIDA [ ELPIDA MEMORY ]
