EDE5104AGSE, EDE5108AGSE
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)
max.
× 4
× 8
Parameter
Symbol Grade
-6C
Unit
mA
Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
TBD
110
105
90
TBD
115
110
95
Operating current
(ACT-PRE)
-6E
-5C
IDD0
-4A
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
-6C
TBD
125
120
105
TBD
130
125
110
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Operating current
(ACT-READ-PRE)
-6E
IDD1
mA
-5C
-4A
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
-6C
TBD
10
10
8
TBD
10
10
8
Precharge power-
down standby current
-6E
IDD2P
mA
mA
mA
-5C
-4A
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
-6C
TBD
25
25
TBD
25
25
Precharge quiet
standby current
-6E
IDD2Q
-5C
-4A
20
20
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-6C
-6E
-5C
-4A
TBD
35
30
TBD
35
30
Idle standby current IDD2N
25
25
-6C
-6E
-5C
-4A
TBD
40
40
TBD
40
40
all banks open;
tCK = tCK (IDD);
CKE is L;
Other control and
address bus inputs
are STABLE;
Data bus inputs are
FLOATING
Fast PDN Exit
MRS(12) = 0
IDD3P-F
mA
mA
35
35
Active power-down
standby current
-6C
-6E
-5C
-4A
TBD
25
25
TBD
25
25
Slow PDN Exit
MRS(12) = 1
IDD3P-S
20
20
all banks open;
-6C
-6E
-5C
-4A
TBD
70
65
TBD
70
65
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active standby
IDD3N
mA
mA
current
60
60
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD),
tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
-6C
-6E
-5C
-4A
TBD
200
170
140
TBD
230
190
150
Operating current
IDD4R
(Burst read operating)
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD),
tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-6C
-6E
-5C
-4A
TBD
190
170
140
TBD
220
190
150
Operating current
(Burst write
operating)
IDD4W
mA
Preliminary Data Sheet E0715E20 (Ver. 2.0)
7
ELPIDA [ ELPIDA MEMORY ]
