EDE5104AGSE, EDE5108AGSE
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA (µBGA)
1
2
3
7
8
9
A
B
NU/ /RDQS
(NC)*
VDD
VSS
VSSQ /DQS VDDQ
DQ6
(NC)*
DQ7
DQS VSSQ
(NC)*
DM/RDQS
VSSQ
(DM)*
C
D
VDDQ
DQ1 VDDQ
VSSQ DQ3
VREF VSS
CKE /WE
VDDQ DQ0 VDDQ
DQ4
(NC)*
DQ5
(NC)*
DQ2 VSSQ
VSSDL CK
E
F
G
H
J
VDD
ODT
VDDL
/RAS
/CAS
A2
/CK
/CS
A0
NC
BA0
A10
BA1
A1
VDD
VSS
VSS
VDD
A3
A7
A5
A9
NC
A6
A11
NC
A4
A8
K
L
A12
A13
(Top view)
Note: ( )* marked pins are for ×4 organization.
Pin name
A0 to A13
BA0, BA1
DQ0 to DQ15
DQS, /DQS
RDQS, /RDQS
/CS
Function
Pin name
ODT
Function
Address inputs
ODT control
Bank select
VDD
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Data input/output
Differential data strobe
Differential data strobe for read
Chip select
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*1
/RAS, /CAS, /WE
CKE
Command input
Clock enable
CK, /CK
Differential clock input
Write data mask
DM
NU*2
Not usable
Notes: 1. Not internally connected with die.
2. Don’t use other than reserved functions.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
3
ELPIDA [ ELPIDA MEMORY ]
