EDE5104AGSE, EDE5108AGSE
Burst Write followed by Precharge
Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clocks + tWR
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge
command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the
burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR2
SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4.
T0
T1
T2
T3
T4
T5
T6
T7
T8
/CK
CK
Posted
WRIT
NOP
PRE
Command
> tWR
=
DQS, /DQS
WL = 3
in0
in1
in2
in3
DQ
Completion of
the Burst Write
Burst Write Followed by Precharge (WL = (RL-1) =3)
T0
T1
T2
T3
T4
T5
T6
T7
T9
/CK
CK
Posted
WRIT
NOP
PRE
Command
> tWR
=
DQS, /DQS
DQ
WL = 4
in0
in1
in2
in3
Completion of
the Burst Write
Burst Write Followed by Precharge (WL = (RL-1) = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T11
/CK
CK
Posted
WRIT
NOP
PRE
Command
DQS, /DQS
DQ
> tWR
=
WL = 4
in0
in1
in2
in3
in4
in5
in6
in7
Completion of
the Burst Write
Burst Write Followed by Precharge (WL = (RL-1) = 4,BL= 8)
Preliminary Data Sheet E0715E20 (Ver. 2.0)
49
ELPIDA [ ELPIDA MEMORY ]
