EDE5104AGSE, EDE5108AGSE
Command Operation
Command Truth Table
The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Previous Current
BA1,
A13 to
A11
A0 to
A10 A9
Function
Symbol cycle
cycle
H
H
H
L
/CS /RAS /CAS /WE BA0
Notes
Mode register set
Extended mode register set
Auto refresh
MRS
H
H
H
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
BA0 = 0 and MRS OP Code
BA0 = 1 and EMRS OP Code
1
EMRS
REF
L
L
L
1
L
L
H
H
×
×
×
×
×
×
×
×
×
×
×
×
L
H
×
×
×
×
×
×
1
Self refresh entry
Self refresh exit
SELF
SELFX
L
L
×
1
H
H
H
H
H
H
H
H
H
×
×
×
H
H
H
H
L
×
1, 6
L
H
L
H
L
×
Single bank precharge
Precharge all banks
Bank activate
PRE
H
H
H
H
H
H
H
H
H
H
H
L
BA
×
1, 2
1
PALL
ACT
L
L
L
H
L
BA
BA
BA
BA
BA
×
Row Address
Column L
Column H
Column L
Column H
1, 2
Write
WRIT
WRITA
READ
READA
NOP
H
H
H
H
H
×
Column 1, 2, 3
Column 1, 2, 3
Column 1, 2, 3
Column 1, 2, 3
Write with auto precharge
Read
L
L
L
H
H
H
×
Read with auto precharge
No operation
L
H
×
×
H
×
H
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
Device deselect
Power down mode entry
DESL
PDEN
×
×
1
L
×
×
×
1, 4
L
H
×
H
×
×
Power down mode exit
PDEX
H
H
×
1, 4
L
H
H
×
Remark: H = VIH. L = VIL. × = VIH or VIL
Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the
clock.
2. Bank select (BA0, BA1), determine which bank is to be operated upon.
3. Burst reads or writes should not be terminated other than specified as ″Reads interrupted by a Read″ in
burst read command [READ] or ″Writes interrupted by a Write″ in burst write command [WRIT].
4. The power down mode does not perform any refresh operations. The duration of power down is therefore
limited by the refresh requirements of the device. One clock delay is required for mode entry and exit.
5. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh.
6. Self refresh exit is asynchronous.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
18
ELPIDA [ ELPIDA MEMORY ]
