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EDE5104AGSE-5C-E 参数 Datasheet PDF下载

EDE5104AGSE-5C-E图片预览
型号: EDE5104AGSE-5C-E
PDF下载: 下载PDF文件 查看货源
内容描述: 512M位DDR2 SDRAM [512M bits DDR2 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 65 页 / 657 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDE5104AGSE, EDE5108AGSE  
-6C, -6E  
667  
-5C  
-4A  
400  
min.  
Frequency (Mbps)  
Parameter  
533  
Symbol min.  
max.  
min.  
max.  
max.  
Unit Notes  
Active bank A to active bank B  
command period  
tRRD  
tWR  
7.5  
15  
7.5  
15  
7.5  
15  
ns  
ns  
Write recovery time  
Auto precharge write recovery +  
precharge time  
(tWR/tCK)+  
(tRP/tCK)  
(tWR/tCK)+  
(tRP/tCK)  
(tWR/tCK)+  
(tRP/tCK)  
tDAL  
tCK  
ns  
1
Internal write to read command  
delay  
tWTR  
tRTP  
7.5  
7.5  
7.5  
7.5  
10  
Internal read to precharge command  
delay  
7.5  
ns  
Exit self refresh to a non-read  
command  
tXSNR  
tRFC + 10  
tRFC + 10  
tRFC + 10  
ns  
Exit self refresh to a read command tXSRD  
200  
2
200  
2
200  
2
tCK  
tCK  
Exit precharge power down to any  
tXP  
non-read command  
Exit active power down to read  
command  
tXARD  
2
2
2
tCK  
3
Exit active power down to read  
command  
tXARDS 7AL  
6 AL  
6 AL  
tCK 2, 3  
(slow exit/low power mode)  
CKE minimum pulse width (high and  
low pulse width)  
tCKE  
3
3
3
tCK  
ns  
Output impedance test driver delay tOIT  
0
12  
0
12  
0
12  
Auto refresh to active/auto refresh  
command time  
tRFC  
105  
105  
105  
ns  
Average periodic refresh interval  
tREFI  
7.8  
3.9  
7.8  
3.9  
7.8  
3.9  
µs  
µs  
ns  
(0°C TC +85°C)  
(+85°C < TC +95°C)  
tREFI  
Minimum time clocks remains ON  
after CKE asynchronously drops low  
tIS + tCK +  
tIH  
tIS + tCK +  
tIH  
tIS + tCK +  
tIH  
tDELAY  
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.  
2. AL: Additive Latency.  
3. MRS A12 bit defines which active power down exit timing to be applied.  
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the  
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.  
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the  
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.  
CK  
DQS  
/CK  
/DQS  
tIS  
tIH  
tIS  
tIH  
tDS tDH  
tDS tDH  
VDDQ  
VDDQ  
VIH (AC)(min.)  
VIH (DC)(min.)  
VREF  
VIH (AC)(min.)  
VIH (DC)(min.)  
VREF  
VIL (DC)(max.)  
VIL (AC)(max.)  
VSS  
VIL (DC)(max.)  
VIL (AC)(max.)  
VSS  
Input Waveform Timing 1 (tDS, tDH)  
Input Waveform Timing 2 (tIS, tIH)  
Preliminary Data Sheet E0715E20 (Ver. 2.0)  
13