EDE1108AFBG
CKE Truth Table
CKE
Previous
Current
Command(n)*3
Current state*2
Power down
cycle (n-1)*1 cycle (n)*1
/CS, /RAS, /CAS, /WE Operation (n)*3
Notes
L
L
H
L
H
L
L
L
×
Maintain power down
11, 13, 15
4, 8, 11, 13
11, 15
L
DESL or NOP
×
Power down exit
Self-refresh
L
Maintain self-refresh
Self-refresh exit
L
DESL or NOP
DESL or NOP
DESL or NOP
SELF
4, 5, 9
Bank Active
H
H
H
Active power down entry
4, 8, 10, 11, 13
All banks idle
Precharge power down entry
Self-refresh entry
4, 8, 10, 11, 13
6, 9, 11, 13
Any state other than
listed above
H
H
Refer to the Command Truth Table
7
Remark: H = VIH. L = VIL. × = Don’t care
Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n−1) was the state of CKE at the previous clock
edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this
document.
5. On self-refresh exit, [DESL] or [NOP] commands must be issued on every clock edge occurring during the
tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied.
6. Self-refresh mode can only be entered from the all banks idle state.
7. Must be a legal command as defined in the command truth table.
8. Valid commands for power down entry and exit are [NOP] and [DESL] only.
9. Valid commands for self-refresh exit are [NOP] and [DESL] only.
10. Power down and self-refresh can not be entered while read or write operations, (extended) mode register
set operations or precharge operations are in progress. See section Power Down and Self-Refresh
Command for a detailed list of restrictions.
11. Minimum CKE high time is 3 clocks; minimum CKE low time is 3 clocks.
12. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh. See section ODT (On Die Termination).
13. The power down does not perform any refresh operations. The duration of power down mode is therefore
limited by the refresh requirements outlined in section automatic refresh command.
14. CKE must be maintained high while the SDRAM is in OCD calibration mode.
15. “×” means “don’t care” (including floating around VREF) in self-refresh and power down. However ODT
must be driven high or low in power down if the ODT function is enabled (bit A2 or A6 set to “1” in EMRS
(1) ).
Preliminary Data Sheet E1430E20 (Ver. 2.0)
30
ELPIDA [ ELPIDA MEMORY ]
