EDE1108AFBG
Command Operation
Command Truth Table
The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Previous Current
A13 to
/CS /RAS /CAS /WE BA0 BA1 BA2 A11
A0 to
A10 A9
Function
Symbol
MRS
cycle
cycle
Notes
1
Mode register set
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
MRS OPCODE
Extended mode
register set (1)
EMRS (1)
OPCODE
EMRS(1)
EMRS(2)
H
H
H
H
H
1
1
Extended mode
register set (2)
EMRS (2)
OPCODE
L
L
L
L
L
H
L
Auto-refresh
REF
H
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
H
H
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
L
H
×
×
×
×
×
×
1
Self-refresh entry
Self-refresh exit
SELF
SELFX
L
L
×
×
1
H
H
H
H
H
H
H
H
H
×
×
×
×
×
1, 6
L
H
L
H
H
H
H
L
H
L
×
×
Single bank precharge
Precharge all banks
Bank activate
PRE
PALL
ACT
H
H
H
H
H
H
H
H
H
H
H
L
BA
×
×
1, 2
1
L
L
×
×
×
L
H
L
BA
BA
BA
BA
BA
×
RA
CA
CA
CA
CA
×
1, 2, 7
Write
WRIT
H
H
H
H
H
×
L
H
L
H
×
×
×
×
×
×
CA 1, 2, 3
CA 1, 2, 3
CA 1, 2, 3
CA 1, 2, 3
Write with auto precharge WRITA
Read READ
Read with auto precharge READA
L
L
L
H
H
H
×
L
No operation
NOP
H
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
Device deselect
DESL
PDEN
×
×
×
1
Power down mode entry
L
×
×
×
×
×
1, 4
L
H
×
H
×
H
×
×
×
Power down mode exit
PDEX
H
H
×
×
1, 4
L
H
H
H
×
×
Remark: H = VIH. L = VIL. × = VIH or VIL. BA = Bank Address, RA = Row Address , CA = Column Address
Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the
clock.
2. Bank select (BA0, BA1 and BA2), determine which bank is to be operated upon.
3. Burst reads or writes should not be terminated other than specified as ″Reads interrupted by a Read″ in
burst read command [READ] or ″Writes interrupted by a Write″ in burst write command [WRIT].
4. The power down mode does not perform any refresh operations. The duration of power down is therefore
limited by the refresh requirements of the device. One clock delay is required for mode entry and exit.
5. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh.
6. Self-refresh exit is asynchronous.
7. 8-bank device sequential bank activation restriction: No more than 4 banks may be activated in a rolling
tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next
integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate
command is issued in clock N, no more than three further activate commands may be issued in clock N+1
through N+9.
Preliminary Data Sheet E1430E20 (Ver. 2.0)
29
ELPIDA [ ELPIDA MEMORY ]
