EDE1104ACSE, EDE1108ACSE, EDE1116ACSE
max.
× 4
× 8
× 16
Parameter
Symbol Grade
-8E
Unit
mA
Test condition
tCK = tCK (IDD);
290
280
270
290
280
270
290
280
270
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Auto-refresh current IDD5
-6E
-5C
Self-Refresh Mode;
-8E
-6E
-5C
10
10
10
10
10
10
10
10
10
CK and /CK at 0V;
CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Self-refresh current
IDD6
IDD7
mA
mA
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),
tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
-8E
-6E
-5C
290
275
260
290
275
260
350
310
290
Operating current
(Bank interleaving)
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
Data Sheet E0975E50 (Ver.5.0)
9
ELPIDA [ ELPIDA MEMORY ]
