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EDD2516ARTA-6B 参数 Datasheet PDF下载

EDD2516ARTA-6B图片预览
型号: EDD2516ARTA-6B
PDF下载: 下载PDF文件 查看货源
内容描述: 256M比特DDR SDRAM [256M bits DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 33 页 / 373 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDD2516ARTA-6B  
-6B  
min.  
2
Parameter  
Symbol  
tMRD  
tRAS  
max.  
Unit  
tCK  
ns  
Notes  
Mode register set command cycle time  
Active to Precharge command period  
42  
120000  
Active to Active/Auto refresh command  
tRC  
60  
72  
ns  
ns  
period  
Auto refresh to Active/Auto refresh command  
period  
tRFC  
Active to Read/Write delay  
Precharge to active command period  
Active to Autoprecharge delay  
Active to active command period  
Write recovery time  
tRCD  
tRP  
18  
ns  
ns  
ns  
ns  
ns  
18  
tRAP  
tRRD  
tWR  
tRCD min.  
12  
15  
Auto precharge write recovery and precharge  
time  
tDAL  
(tWR/tCK) + (tRP/tCK)  
tCK  
13  
Internal write to Read command delay  
tWTR  
tREF  
1
tCK  
µs  
Average periodic refresh interval  
7.8  
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter  
definitions, see ‘Timing Waveforms’ section.  
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal  
transition is defined to occur when the signal level crossing VTT.  
3. The timing reference level is VTT.  
4. Output valid window is defined to be the period between two successive transition of data out or DQS  
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.  
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The  
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage  
level, but specify when the device output stops driving.  
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This  
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins  
driving.  
7. Input valid windows is defined to be the period between two successive transition of data input or DQS  
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.  
8. The timing reference level is VREF.  
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific  
reference voltage to judge this transition is not given.  
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not  
assured.  
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these  
values are 10% of tCK.  
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than  
0.4V/400 cycle.  
13. tDAL = (tWR/tCK)+(tRP/tCK)  
For each of the terms above, if not already an integer, round to the next highest integer.  
Example: For –6B Speed at CL = 2.5, tCK = 6ns, tWR = 15ns and tRP= 18ns,  
tDAL = (15ns/6ns) + (18ns/6ns) = (3) + (3)  
tDAL = 6 clocks  
Data Sheet E0848E10 (Ver. 1.0)  
8