欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDD2516ARTA-6B 参数 Datasheet PDF下载

EDD2516ARTA-6B图片预览
型号: EDD2516ARTA-6B
PDF下载: 下载PDF文件 查看货源
内容描述: 256M比特DDR SDRAM [256M bits DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 33 页 / 373 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDD2516ARTA-6B的Datasheet PDF文件第6页浏览型号EDD2516ARTA-6B的Datasheet PDF文件第7页浏览型号EDD2516ARTA-6B的Datasheet PDF文件第8页浏览型号EDD2516ARTA-6B的Datasheet PDF文件第9页浏览型号EDD2516ARTA-6B的Datasheet PDF文件第11页浏览型号EDD2516ARTA-6B的Datasheet PDF文件第12页浏览型号EDD2516ARTA-6B的Datasheet PDF文件第13页浏览型号EDD2516ARTA-6B的Datasheet PDF文件第14页  
EDD2516ARTA-6B  
Timing Parameter Measured in Clock Cycle  
Number of clock cycle  
tCK  
6ns  
Parameter  
Symbol  
min.  
max.  
Unit  
tCK  
tCK  
tCK  
Write to pre-charge command delay (same bank) tWPD  
Read to pre-charge command delay (same bank) tRPD  
4 + BL/2  
BL/2  
Write to read command delay (to input all data)  
Burst stop command to write command delay  
(CL = 2)  
(CL = 2.5)  
Burst stop command to DQ High-Z  
(CL = 2)  
tWRD  
tBSTW  
tBSTW  
tBSTZ  
tBSTZ  
2 + BL/2  
2
2
tCK  
tCK  
tCK  
tCK  
3
2
(CL = 2.5)  
2.5  
2.5  
Read command to write command delay  
(to output all data)  
(CL = 2)  
tRWD  
2 + BL/2  
tCK  
(CL = 2.5)  
Pre-charge command to High-Z  
(CL = 2)  
tRWD  
tHZP  
3 + BL/2  
2
2
tCK  
tCK  
(CL = 2.5)  
tHZP  
2.5  
1
2.5  
1
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
Write command to data in latency  
Write recovery  
tWCD  
tWR  
3
0
DM to data in latency  
tDMD  
tMRD  
tSNR  
tSRD  
tPDEN  
tPDEX  
0
Mode register set command cycle time  
Self refresh exit to non-read command  
Self refresh exit to read command  
Power down entry  
2
1
12  
200  
1
Power down exit to command input  
1
Data Sheet E0848E10 (Ver. 1.0)  
10