EDD2516ARTA-6B
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
6ns
Parameter
Symbol
min.
max.
—
Unit
tCK
tCK
tCK
Write to pre-charge command delay (same bank) tWPD
Read to pre-charge command delay (same bank) tRPD
4 + BL/2
BL/2
—
Write to read command delay (to input all data)
Burst stop command to write command delay
(CL = 2)
(CL = 2.5)
Burst stop command to DQ High-Z
(CL = 2)
tWRD
tBSTW
tBSTW
tBSTZ
tBSTZ
2 + BL/2
—
2
—
—
2
tCK
tCK
tCK
tCK
3
2
(CL = 2.5)
2.5
2.5
Read command to write command delay
(to output all data)
(CL = 2)
tRWD
2 + BL/2
—
tCK
(CL = 2.5)
Pre-charge command to High-Z
(CL = 2)
tRWD
tHZP
3 + BL/2
2
—
2
tCK
tCK
(CL = 2.5)
tHZP
2.5
1
2.5
1
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Write command to data in latency
Write recovery
tWCD
tWR
3
—
0
DM to data in latency
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
0
Mode register set command cycle time
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
2
—
—
—
1
12
200
1
Power down exit to command input
1
—
Data Sheet E0848E10 (Ver. 1.0)
10
ELPIDA [ ELPIDA MEMORY ]
