EDD2516ARTA-6B
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter
Symbol
CI1
Pins
min.
2.0
2.0
—
typ.
—
—
—
—
—
—
max.
3.0
3.0
0.25
0.5
5
Unit
pF
pF
pF
pF
pF
pF
Notes
Input capacitance
CK, /CK
1
CI2
All other input pins
CK, /CK
1
Delta input capacitance
Cdi1
Cdi2
CI/O
Cdio
1
All other input-only pins
DQ, DM, DQS
DQ, DM, DQS
—
1
Data input/output capacitance
Delta input/output capacitance
4.0
—
1, 2,
1
0.5
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V,
TA = +25°C.
2. DOUT circuits are disabled.
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-6B
Parameter
Symbol
tCK
min.
7.5
max.
12
Unit
ns
Notes
10
Clock cycle time
(CL = 2)
(CL = 2.5)
tCK
tCH
tCL
tHP
6
12
ns
CK high-level width
CK low-level width
CK half period
0.45
0.55
0.55
—
tCK
tCK
tCK
0.45
min (tCH, tCL)
DQ output access time from
CK, /CK
tAC
–0.7
0.7
ns
2, 11
DQS output access time from CK, /CK
tDQSCK
tDQSQ
tQH
–0.6
—
0.6
0.45
—
ns
2, 11
3
DQS to DQ skew
ns
DQ/DQS output hold time from DQS
Data hold skew factor
tHP – tQHS
—
ns
tQHS
1
ns
Data-out high-impedance time from CK, /CK tHZ
Data-out low-impedance time from CK, /CK tLZ
–0.7
–0.7
0.9
0.7
0.7
1.1
0.7
—
ns
5, 11
6, 11
ns
Read preamble
tRPRE
tCK
tCK
ns
Read postamble
tRPST
tDS
0.3
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
0.50
0.50
1.75
0
8
8
7
tDH
—
ns
tDIPW
tWPRES
tWPRE
tWPST
—
ns
—
ns
0.25
0.4
—
tCK
tCK
Write postamble
0.6
9
Write command to first DQS latching
transition
tDQSS
0.75
1.25
tCK
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
tDSS
tDSH
tDQSH
tDQSL
tIS
0.2
—
—
—
—
—
—
—
tCK
tCK
tCK
tCK
ns
0.2
0.35
0.35
0.75
0.75
2.2
DQS input low pulse width
Address and control input setup time
Address and control input hold time
Address and control input pulse width
8
8
7
tIH
ns
tIPW
ns
Data Sheet E0848E10 (Ver. 1.0)
7
ELPIDA [ ELPIDA MEMORY ]
