DATA SHEET
256M bits DDR SDRAM
EDD2516ARTA-6B (16M words × 16 bits)
Specifications
Pin Configurations
• Density: 256M bits
/xxx indicates active low signal.
• Organization
66-pin Plastic TSOP(II)
4M words × 16 bits × 4 banks
• Package: 66-pin plastic TSOP (II)
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data rate: 333Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
• /CAS Latency (CL): 2, 2.5
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
1
2
3
4
5
6
7
8
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8µs
• Operating ambient temperature range
TA = 0°C to +70°C
NC
BA0
BA1
Features
A10(AP)
A0
• Double-data-rate architecture; two data transfers per
A1
A2
A3
VDD
A5
A4
VSS
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
(Top view)
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
A0 to A12
BA0, BA1
Address input
Bank select address
• Data inputs, outputs, and DM are synchronized with
DQS
DQ0 to DQ15 Data-input/output
UDQS/LDQS Input and output data strobe
• DQS is edge-aligned with data for READs; center-
/CS
Chip select
aligned with data for WRITEs
/RAS
/CAS
/WE
Row address strobe command
Column address strobe command
Write enable
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
UDM/LDM
CK
Input mask
Clock input
transitions
• Commands entered on each positive CK edge; data
/CK
CKE
Differential clock input
Clock enable
and data mask referenced to both edges of DQS
VREF
VDD
VSS
VDDQ
VSSQ
NC
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
• Data mask (DM) for write data
Document No. E0848E10 (Ver. 1.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
ELPIDA [ ELPIDA MEMORY ]
