EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Precharge command
(/CS, /RAS, /WE= Low, /CAS = High)
Fig.4 Precharge command
CLK
CKE
/CS
H
This command begins precharge operation of the bank selected by BA0, BA1
and A10. When A10 is High, all banks are precharged, regardless of BA0 and
BA1.
/RAS
/CAS
/WE
When A10 is Low, only the bank selected by BA0 and BA1 is precharged.
After this command, the EDD12xxALTA can't accept the activate command to
the precharging bank during tRP (precharge to activate command period).
This command can terminate the current burst operation.
BA0, BA1
A10
This command corresponds to a conventional DRAM's /RAS rising.
(Precharge select)
Add
Read command
Fig.5 Read command
(/CS, /CAS = Low, /RAS, /WE = High)
CLK
CKE
H
This command begins the burst read operation. The bank and the burst start
column address are selected by BA0 and BA1 and by A0 through A11
respectively.
/CS
/RAS
Read data is available after /CAS latency requirements which have been met.
And it is synchronized with DQS.
/CAS
/WE
BA0, BA1
A10
(Auto precharge select)
Add
Col.
Write command
Fig.6 Write command
(/CS, /CAS, /WE = Low, /RAS = High)
CLK
CKE
/CS
H
This command begins burst write operation. The bank and the burst start
column address are selected by BA0 and BA1 and by A0 through A11
respectively.
/RAS
Write data must be input by DQ0 through DQ15. Byte mask data must be input
by DM, LDM, and UDM. Both data must be synchronized with DQS that is
inputted after this command.
/CAS
/WE
BA0, BA1
A10
(Auto precharge select)
Add
Col.
12
Preliminary Data Sheet E0136E30
ELPIDA [ ELPIDA MEMORY ]
