EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
2. Commands
Extended mode register set command
Fig.1 Extended mode register
set command
(/CS, /RAS, /CAS, /WE Low)
CLK
The EDD12xxALTA has an extended mode register that defines enabling or
disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data
input pins.
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
After power on, the extended mode register set command must be executed for
enabling or disabling DLL.
The extended mode register can be set only when all banks are in idle state.
During tMRD, the EDD12xxALTA can not accept any other commands.
Add
Mode register set command
Fig.2 Mode register set command
(/CS, /RAS, /CAS, /WE Low)
CLK
CKE
/CS
H
The EDD12xxALTA has a mode register that defines how the device operates.
In this command, A0 through A11, BA0 and BA1 are the data input pins.
After power on, the mode register set command must be executed to initialize the
device.
/RAS
/CAS
/WE
The mode register can be set only when all banks are in idle state.
During tMRD, the EDD12xxALTA can not accept any other commands.
BA0,BA1
A10
Add
Bank activate command
Fig.3 Bank activate command
(/CS, /RAS = Low, /CAS, /WE = High)
CLK
CKE
/CS
H
The EDD12xxALTA has four banks, each with 4,096 rows.
This command activates the bank and the row address selected by BA0 and
BA1, and by A0 through A11 respectively.
/RAS
/CAS
/WE
This command corresponds to a conventional DRAM's /RAS falling.
BA0,BA1
A10
Row
Row
Add
11
Preliminary Data Sheet E0136E30
ELPIDA [ ELPIDA MEMORY ]
