EBE51UD8AGWA
-5C
533
min.
15
Frequency (Mbps)
Parameter
Symbol
tWR
max.
Unit
ns
Notes
1
Write recovery time
(tWR/tCK)+
(tRP/tCK)
Auto precharge write recovery + precharge time
tDAL
tCK
Internal write to read command delay
Internal read to precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to a read command
tWTR
tRTP
7.5
ns
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
ns
tCK
Exit precharge power-down to any non-read
command
Exit active power-down to read command
Exit active power-down to read command
(slow exit/low power mode)
tXP
2
tCK
tCK
tCK
tXARD
tXARDS
2
3
6 − AL
2, 3
CKE minimum pulse width (high and low pulse width) tCKE
3
tCK
ns
Output impedance test driver delay
tOIT
0
12
12
MRS command to ODT update delay
tMOD
tRFC
0
ns
Auto refresh to active/auto refresh command time
105
ns
Average periodic refresh interval
tREFI
7.8
3.9
µs
µs
ns
(0°C ≤ TC ≤ +85°C)
(+85°C < TC ≤ +95°C)
Minimum time clocks remains ON after CKE
asynchronously drops low
tREFI
tIS + tCK +
tIH
tDELAY
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
CK
DQS
/CK
/DQS
tIS
tIH
tIS
tIH
tDS tDH
tDS tDH
VDDQ
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Preliminary Data Sheet E0921E10 (Ver. 1.0)
19
ELPIDA [ ELPIDA MEMORY ]
