EBE51UD8AGWA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V) [DDR2 533]
(DDR2 SDRAM Component Specification)
-5C
533
min.
4
Frequency (Mbps)
Parameter
Symbol
CL
max.
5
Unit
tCK
ns
Notes
/CAS latency
Active to read or write command delay
Precharge command period
Active to active/auto refresh command time
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tRCD
tRP
15
15
ns
tRC
60
ns
tAC
−500
−450
0.45
0.45
+500
+450
0.55
0.55
ps
tDQSCK
tCH
ps
tCK
tCK
CK low-level width
tCL
min.
CK half period
tHP
ps
ps
ps
(tCL, tCH)
Clock cycle time
DQ and DM input hold time
(differential strobe)
tCK
3750
8000
tDH (base)
225
5
4
DQ and DM input hold time
(single-ended strobe)
DQ and DM input setup time
(differential strobe)
DQ and DM input setup time
(single-ended strobe)
tDH1 (base) –25
tDS (base) 100
tDS1 (base) –25
ps
ps
ps
Control and Address input pulse width for each input tIPW
0.6
tCK
tCK
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK,/CK
Data-out low-impedance time from CK,/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDIPW
tHZ
0.35
tAC max.
tAC max.
300
tLZ
tAC min.
ps
tDQSQ
tQHS
tQH
ps
400
ps
DQ/DQS output hold time from DQS
tHP – tQHS
ps
DQS latching rising transitions to associated clock
edges
tDQSS
−0.25
+0.25
tCK
DQS input high pulse width
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDSH
0.2
tMRD
2
tWPST
tWPRE
tIH (base)
tIS (base)
tRPRE
tRPST
tRAS
0.4
0.6
Write preamble
0.35
375
250
0.9
Address and control input hold time
Address and control input setup time
Read preamble
5
4
ps
1.1
tCK
tCK
ns
Read postamble
0.4
0.6
Active to precharge command
Active to auto-precharge delay
Active bank A to active bank B command period
45
70000
tRAP
tRCD min.
7.5
ns
tRRD
ns
Preliminary Data Sheet E0921E10 (Ver. 1.0)
18
ELPIDA [ ELPIDA MEMORY ]
