PRELIMINARY DATA SHEET
512MB Unbuffered DDR2 SDRAM DIMM
EBE51UD8AGWA (64M words × 64 bits, 1 Rank)
Specifications
Features
• Density: 512MB
• Organization
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
64M words × 64 bits, 1 rank
prefetch pipelined architecture
• Mounting 8 pieces of 512M bits DDR2 SDRAM
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
sealed in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
• DQS is edge-aligned with data for READs; center-
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps/533Mbps (max.)
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
(components)
• Data mask (DM) for write data
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Precharge: auto precharge option for each burst
• /DQS can be disabled for single-ended Data Strobe
access
operation
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Document No. E0921E10 (Ver. 1.0)
Date Published June 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006
ELPIDA [ ELPIDA MEMORY ]
