EBE51UD8AGWA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Minimum row active to row active
28
29
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1EH
3CH
7.5ns
15ns
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
Minimum active to precharge time
30
31
32
(tRAS)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
2DH
80H
20H
25H
27H
37H
10H
45ns
-6E, -5C
Module rank density
Address and command setup time
before clock (tIS)
-6E
512M bytes
0.20ns*1
0.25ns*1
0.27ns*1
0.37ns*1
0.10ns*1
-5C
Address and command hold time after
clock (tIH)
-6E
33
-5C
Data input setup time before clock
(tDS)
-6E, -5C
Data input hold time after clock (tDH)
-6E
-5C
34
35
0
0
0
1
0
1
1
1
17H
0.17ns*1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
0
22H
3CH
0.22ns*1
15ns*1
36
37
Write recovery time (tWR)
Internal write to read command delay
(tWTR)
-6E, -5C
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
7.5ns*1
7.5ns*1
38
0
0
0
1
1
1
1
0
1EH
39
40
Memory analysis probe characteristics 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00H
00H
TBD
Extension of Byte 41 and 42
0
Undefined
Active command period (tRC)
-6E, -5C
41
0
0
1
1
1
1
0
0
3CH
60ns*1
Auto refresh to active/
42
43
44
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
69H
80H
18H
1EH
22H
28H
105ns*1
8ns*1
Auto refresh command cycle (tRFC)
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6E
0.24ns*1
0.30ns*1
0.34ns*1
0.40ns*1
-5C
Data hold skew (tQHS)
-6E
-5C
45
Preliminary Data Sheet E0921E10 (Ver. 1.0)
6
ELPIDA [ ELPIDA MEMORY ]
