EBE51RD8AJFA
-5C
-4A
DDR2-400 (3-3-3)
Speed bin
DDR2-533 (4-4-4)
Parameter
Symbol
tRAP
min.
max.
min.
max.
Unit
ns
Notes
Active to auto-precharge delay
tRCD min.
tRCD min.
Active bank A to active bank B command
period
tRRD
7.5
7.5
ns
/CAS to /CAS command delay
Write recovery time
tCCD
tWR
2
2
tCK
ns
15
15
Auto precharge write recovery + precharge
time
WR +
RU(tRP/tCK)
WR +
RU(tRP/tCK)
tDAL
tCK
1, 9
14
Internal write to read command delay
tWTR
7.5
10
ns
Internal read to precharge command delay tRTP
7.5
7.5
ns
Exit self-refresh to a non-read command
Exit self-refresh to a read command
tXSNR
tRFC + 10
200
tRFC + 10
200
ns
tXSRD
tXP
tCK
Exit precharge power-down to any non-read
command
2
2
tCK
tCK
tCK
Exit active power-down to read command
tXARD
tXARDS
2
2
3
Exit active power-down to read command
(slow exit/low power mode)
6 − AL
6 − AL
2, 3
CKE minimum pulse width (high and low
pulse width)
tCKE
3
3
tCK
Output impedance test driver delay
MRS command to ODT update delay
tOIT
0
0
12
12
0
0
12
12
ns
ns
tMOD
Auto-refresh to active/auto-refresh command
time
tRFC
105
105
ns
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI
7.8
3.9
7.8
3.9
µs
µs
ns
(+85°C < TC ≤ +95°C)
tREFI
Minimum time clocks remains ON after CKE
asynchronously drops low
tIS + tCK +
tIH
tIS + tCK +
tIH
tDELAY
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power-down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test.
CK
DQS
/CK
/DQS
tIS
tIH
tIS
tIH
tDS tDH
tDS tDH
VDDQ
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E1036E30 (Ver. 3.0)
20
ELPIDA [ ELPIDA MEMORY ]
