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EBE51RD8AJFA-6E-E 参数 Datasheet PDF下载

EBE51RD8AJFA-6E-E图片预览
型号: EBE51RD8AJFA-6E-E
PDF下载: 下载PDF文件 查看货源
内容描述: 注册512MB DDR2 SDRAM DIMM [512MB Registered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 30 页 / 246 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE51RD8AJFA  
AC Characteristics [DDR2-533, 400]  
-5C  
-4A  
DDR2-400 (3-3-3)  
Speed bin  
DDR2-533 (4-4-4)  
Parameter  
Symbol  
tRCD  
tRP  
min.  
15  
max.  
min.  
15  
max.  
Unit  
ns  
Notes  
Active to read or write command delay  
Precharge command period  
15  
15  
ns  
Active to active/auto-refresh command time tRC  
60  
55  
ns  
DQ output access time from CK, /CK  
DQS output access time from CK, /CK  
CK high-level width  
tAC  
500  
+500  
+450  
0.55  
0.55  
600  
500  
0.45  
0.45  
+600  
+500  
0.55  
0.55  
ps  
tDQSCK 450  
ps  
tCH  
tCL  
0.45  
0.45  
tCK  
tCK  
CK low-level width  
Min.  
(tCL, tCH)  
Min.  
(tCL, tCH)  
CK half period  
tHP  
tCK  
ps  
ps  
Clock cycle time  
(CL = 6)  
3750  
8000  
5000  
8000  
(CL = 5)  
(CL = 4)  
(CL = 3)  
tCK  
tCK  
tCK  
3750  
3750  
5000  
8000  
8000  
8000  
5000  
5000  
5000  
8000  
8000  
8000  
ps  
ps  
ps  
DQ and DM input hold time  
(differential strobe)  
tDH (base) 225  
275  
+25  
150  
+25  
ps  
5
4
DQ and DM input hold time  
(single-ended strobe)  
tDH1  
–25  
ps  
(base)  
DQ and DM input setup time  
(differential strobe)  
tDS (base) 100  
ps  
DQ and DM input setup time  
(single-ended strobe)  
tDS1  
–25  
ps  
(base)  
Control and Address input pulse width for  
each input  
tIPW  
0.6  
0.6  
tCK  
DQ and DM input pulse width for each input tDIPW  
Data-out high-impedance time from CK,/CK tHZ  
Data-out low-impedance time from CK,/CK tLZ  
0.35  
0.35  
tCK  
ps  
tAC max.  
tAC max.  
tAC max.  
tAC max.  
tAC min.  
tAC min.  
ps  
DQS-DQ skew for DQS and associated DQ  
signals  
tDQSQ  
300  
400  
350  
450  
ps  
DQ hold skew factor  
tQHS  
tQH  
ps  
ps  
DQ/DQS output hold time from DQS  
tHP – tQHS  
tHP – tQHS  
DQS latching rising transitions to associated  
clock edges  
tDQSS  
0.25  
+0.25  
0.25  
+0.25  
tCK  
DQS input high pulse width  
DQS input low pulse width  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
Write postamble  
tDQSH  
tDQSL  
tDSS  
0.35  
0.35  
0.2  
0.2  
2
0.35  
0.35  
0.2  
0.2  
2
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ps  
tDSH  
tMRD  
tWPST  
tWPRE  
0.4  
0.35  
0.6  
0.4  
0.35  
475  
350  
0.9  
0.4  
40  
0.6  
Write preamble  
Address and control input hold time  
Address and control input setup time  
Read preamble  
tIH (base) 375  
tIS (base) 250  
5
4
ps  
tRPRE  
tRPST  
tRAS  
0.9  
0.4  
45  
1.1  
1.1  
tCK  
tCK  
ns  
Read postamble  
0.6  
0.6  
Active to precharge command  
70000  
70000  
Data Sheet E1036E30 (Ver. 3.0)  
19  
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