EBE21EE8ABFA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V) [DDR2 533, 400]
(DDR2 SDRAM Component Specification)
-5C
533
min.
4
-4A
400
min.
3
Frequency (Mbps)
Parameter
Symbol
max.
5
max.
5
Unit
tCK
ns
Notes
/CAS latency
CL
Active to read or write command delay
Precharge command period
tRCD
tRP
15
15
15
15
ns
Active to active/auto refresh command time tRC
60
55
ns
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tAC
−500
+500
+450
0.55
0.55
−600
−500
0.45
0.45
+600
+500
0.55
0.55
ps
tDQSCK −450
ps
tCH
tCL
0.45
0.45
tCK
tCK
CK low-level width
min.
(tCL, tCH)
min.
(tCL, tCH)
CK half period
tHP
tCK
ps
ps
ps
Clock cycle time
3750
8000
5000
8000
DQ and DM input hold time
(differential strobe)
tDH (base) 225
275
5
4
DQ and DM input hold time
(single-ended strobe)
tDH1
–25
+25
150
+25
ps
(base)
DQ and DM input setup time
(differential strobe)
tDS (base) 100
ps
DQ and DM input setup time
(single-ended strobe)
tDS1
–25
ps
(base)
Control and Address input pulse width for
each input
tIPW
0.6
0.6
tCK
DQ and DM input pulse width for each input tDIPW
Data-out high-impedance time from CK,/CK tHZ
Data-out low-impedance time from CK,/CK tLZ
0.35
0.35
tCK
ps
tAC max.
tAC max.
tAC max.
tAC max.
tAC min.
tAC min.
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
300
400
350
450
ps
DQ hold skew factor
tQHS
tQH
ps
ps
DQ/DQS output hold time from DQS
tHP – tQHS
tHP – tQHS
DQS latching rising transitions to associated
clock edges
tDQSS
−0.25
+0.25
−0.25
+0.25
tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
0.35
0.35
0.2
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
tDSH
0.2
tMRD
2
tWPST
tWPRE
0.4
0.35
0.6
0.4
0.6
Write preamble
0.35
475
350
0.9
Address and control input hold time
Address and control input setup time
Read preamble
tIH (base) 375
tIS (base) 250
5
4
ps
tRPRE
tRPST
tRAS
0.9
1.1
1.1
tCK
tCK
ns
Read postamble
0.4
0.6
0.4
0.6
Active to precharge command
Active to auto-precharge delay
45
70000
40
70000
tRAP
tRCD min.
tRCD min.
ns
Preliminary Data Sheet E0907E10 (Ver. 1.0)
20
ELPIDA [ ELPIDA MEMORY ]
