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EBE10AD4AGFA 参数 Datasheet PDF下载

EBE10AD4AGFA图片预览
型号: EBE10AD4AGFA
PDF下载: 下载PDF文件 查看货源
内容描述: 注册1GB DDR2 SDRAM DIMM [1GB Registered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 23 页 / 199 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE10AD4AGFA  
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)  
Parameter  
Symbol  
tAOND  
min.  
2
max.  
2
Unit Notes  
tCK  
ODT turn-on delay  
ODT turn-on  
-6E  
tAON  
tAC(min)  
tAC(max) + 700  
ps  
1
1
-5C, -4A  
tAON  
tAC(min)  
tAC(max) + 1000  
ps  
ODT turn-on (power down mode)  
ODT turn-off delay  
tAONPD  
tAOFD  
tAOF  
tAC(min) + 2000  
2tCK + tAC(max) + 1000  
ps  
2.5  
2.5  
tCK  
ps  
ODT turn-off  
tAC(min)  
tAC(max) + 600  
2
ODT turn-off (power down mode)  
ODT to power down entry latency  
ODT power down exit latency  
tAOFPD  
tANPD  
tAXPD  
tAC(min) + 2000  
2.5tCK + tAC(max) + 1000  
ps  
3
8
3
8
tCK  
tCK  
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.  
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.  
2. ODT turn off time min is when the device starts to turn off ODT resistance.  
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.  
AC Input Test Conditions  
Parameter  
Symbol  
Value  
0.5 × VDDQ  
1.0  
Unit  
V
Notes  
1
Input reference voltage  
VREF  
Input signal maximum peak to peak swing  
Input signal maximum slew rate  
VSWING(max.)  
SLEW  
V
1
1.0  
V/ns  
2, 3  
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the  
device under test.  
2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC)  
(min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in  
the below figure.  
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive  
transitions and VIH(AC) to VIL(AC) on the negative transitions.  
Start of rising edge input timing  
Start of falling edge input timing  
VDDQ  
VIH (AC)(min.)  
VIH (DC)(min.)  
VREF  
VSWING(max.)  
VIL (DC)(max.)  
VIL (AC)(max.)  
VSS  
TF  
TR  
VIH (DC)(min.)  
VIL (AC)(max.)  
VIH (AC) min.  
VIL (DC)(max.)  
Falling slew =  
Rising slew =  
TF  
TR  
AC Input Test Signal Wave forms  
Measurement point  
DQ  
VTT  
RT =25 Ω  
Output Load  
Preliminary Data Sheet E0865E11 (Ver. 1.1)  
18  
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