EBD21RD4ABNA
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
device
256 byte
2
3
4
5
6
7
8
Memory type
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
0
1
1
0
0
0
0
0
07H
0DH
0CH
02H
48H
00H
04H
SDRAM DDR
Number of row address
Number of column address
Number of DIMM banks
Module data width
13
12
2
72 bits
0 (+)
Module data width continuation
Voltage interface level of this assembly 0
SSTL 2.5V
DDR SDRAM cycle time, CL = X
-7A, -7B
9
0
1
0
1
1
1
1
1
0
1
0
0
0
1
0
1
0
0
0
1
0
1
75H
A0H
75H
CL = 2.5*3
-10
1
0
SDRAM access from clock (tAC)
-7A, -7B
10
0.75ns*3
-10
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
80H
02H
0.8ns*3
ECC
11
12
DIMM configuration type
7.8 µs
Self refresh
Refresh rate/type
1
0
0
0
0
0
1
0
82H
13
14
Primary SDRAM width
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
04H
04H
× 4
× 4
Error checking SDRAM width
SDRAM device attributes:
Minimum clock delay back-to-back
column access
15
0
0
0
0
0
0
0
1
01H
1 CLK
SDRAM device attributes:
Burst length supported
16
17
18
19
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0EH
04H
0CH
01H
02H
2, 4, 8
SDRAM device attributes: Number of
banks on SDRAM device
4
SDRAM device attributes:
/CAS latency
2, 2.5
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
0
1
21
22
SDRAM module attributes
0
1
0
1
1
0
0
0
0
0
1
0
1
0
0
0
26H
C0H
Registered
0.2V
SDRAM device attributes: General
Minimum clock cycle time at CLX - 0.5
-7A
23
0
1
1
0
1
1
1
0
0
0
1
0
0
0
1
0
75H
A0H
CL = 2*3
-7B, -10
Maximum data access time (tAC) from
clock at CLX - 0.5
-7A, -7B
24
0
1
1
1
0
1
0
1
75H
0.75ns*3
0.8ns*3
-10
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
80H
00H
25
26
27
28
29
Minimum clock cycle time at CLX - 1
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
00H
50H
3CH
50H
Minimum row precharge time (tRP)
20ns
15ns
20ns
Minimum row active to row active
delay (tRRD)
Minimum /RAS to /CAS delay (tRCD)
Preliminary Data Sheet E0273E20 (Ver. 2.0)
5
ELPIDA [ ELPIDA MEMORY ]
