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E1750E31 参数 Datasheet PDF下载

E1750E31图片预览
型号: E1750E31
PDF下载: 下载PDF文件 查看货源
内容描述: 2G位DDR3L SDRAM [2G bits DDR3L SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 32 页 / 606 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDJ2108EEBG, EDJ2116EEBG  
Table 14: IDD7 Measurement-Loop Pattern  
CK,  
/CK  
Sub  
-Loop number  
Cycle  
Com-  
mand  
A11  
A7 A3 A0  
CKE  
/CS /RAS /CAS /WE ODT BA*3 -Am A10 -A9 -A6 -A2 Data*2  
0
ACT  
RDA  
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
00000000  
0
2
Repeat above D Command until nRRD 1  
nRRD  
ACT  
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
F
F
F
0
0
0
nRRD + 1 RDA  
00110011  
1
nRRD + 2  
D
Repeat above D Command until 2 × nRRD 1  
2
3
2 × nRRD Repeat Sub-Loop 0, but BA= 2  
3 × nRRD Repeat Sub-Loop 1, but BA= 3  
D
1
0
0
0
0
3
0
0
0
F
0
4
5
6
4 × nRRD  
Assert and repeat above D Command until nFAW 1, if necessary  
Repeat Sub-Loop 0, but BA= 4  
nFAW  
nFAW  
Repeat Sub-Loop 1, but BA= 5  
Repeat Sub-Loop 0, but BA= 6  
Repeat Sub-Loop 1, but BA= 7  
+ nRRD  
nFAW  
7
8
9
+ 2 × nRRD  
nFAW  
+ 3 × nRRD  
D
1
0
0
0
0
7
0
0
0
F
0
0
nFAW  
+ 4 × nRRD  
Assert and repeat above D Command until 2 × nFAW 1, if necessary  
2 × nFAW  
+ 0  
ACT  
0
0
1
1
0
0
0
0
0
F
2 × nFAW  
+ 1  
Toggling Static H  
RDA  
D
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
F
F
0
0
00110011  
10  
11  
2 × nFAW  
+ 2  
Repeat above D Command until 2 × nFAW + nRRD 1  
2 × nFAW  
+ nRRD  
ACT  
0
0
1
1
0
1
0
0
0
0
0
2 × nFAW  
+ nRRD + 1  
RDA  
D
0
1
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
00000000  
2 × nFAW  
+ nRRD + 2  
Repeat above D Command until 2 × nFAW + 2 × nRRD 1  
2 × nFAW  
+2 × nRRD  
2 × nFAW  
+ 3 × nRRD  
12  
13  
Repeat Sub-Loop 10, but BA= 2  
Repeat Sub-Loop 11, but BA= 3  
D
1
0
0
0
0
3
0
0
0
0
0
2 × nFAW  
+ 4 × nRRD  
14  
15  
16  
Assert and repeat above D Command until 3 × nFAW 1, if necessary  
3 × nFAW Repeat Sub-Loop 10, but BA= 4  
3 × nFAW  
Repeat Sub-Loop 11, but BA= 5  
+nRRD  
3 × nFAW  
17  
18  
19  
Repeat Sub-Loop 10, but BA= 6  
+ 2 × nRRD  
3 × nFAW  
Repeat Sub-Loop 11, but BA= 7  
+ 3 × nRRD  
D
1
0
0
0
0
7
0
0
0
0
0
3 × nFAW  
+ 4 × nRRD  
Assert and repeat above D Command until 4 × nFAW 1, if necessary  
Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL.  
2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL.  
3. BA: BA0 to BA2.  
4. Am: m means Most Significant Bit (MSB) of Row address.  
Data Sheet E1750E31 (Ver. 3.1)  
18  
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