GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
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7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical non-
volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for
Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable
for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status
Register command to change the volatile Status Register bit values.
Figure 4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
High-Z
SI
SO
Figure 4a. Write Enable for Volatile Status Register Sequence Diagram (QPI)
CS#
0
1
SCLK
Command
50H
IO0
IO1
IO2
IO3
Rev.1.0
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