GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
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Fast Read (0BH) in QPI mode
The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is
configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with
different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the
Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8.
Figure 8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13
SCLK
IOs switch from
Input to output
Command
0BH
Dummy*
A23-16 A15-8 A7-0
IO0
IO1
IO2
IO3
20 16 12
8
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
21 17 13
9
22 18 14 10
23 19 15 11
Byte1 Byte2
*"Set Read Parameters" Command (C0H)
can set the number of dummy clocks
7.8. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in followed Figure9. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out.
Figure 9. Dual Output Fast Read Sequence Diagram
Rev.1.0
59 - 21
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