DTL1N60/DTP1N60/DTU1N60
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Peak Diode Recovery dV/dt Test Circuit
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Circuit layout considerations
D.U.T.
•
•
•
Low stray inductance
Ground plane
Low leakage inductance
current transformer
-
+
-
-
+
Rg
•
•
•
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
+
-
VDD
• D.U.T. - device under test
Driver gate drive
P.W.
P.W.
Period
Period
D =
VGS = 10 Va
D.U.T. lSD waveform
D.U.T. VDS waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
ISD
Ripple ≤ 5 %
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
7
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