PERFORMANCE
The following table gives a survey about
the Core performance in the ALTERA® de-
vices after Place & Route (all key features
have been included):
Speed
Logic Cells
F
max
grade
CYCLONE
-6
79
354 MHz
CYCLONE2
-6
87
329 MHz
STRATIX
-5
79
386 MHz
STRATIX2
-3
84
422 MHz
STRATIXGX
-5
79
382 MHz
MERCURY
-5
95
347 MHz
EXCALIBUR
-1
82
224 MHz
APEX2A
-7
82
320 MHz
APEX20KC
-7
82
241 MHz
APEX20KE
-1
82
202 MHz
APEX20K
-1
82
140 MHz
ACEX1K
-1
87
196 MHz
FLEX10KE
-1
87
204 MHz
MAX2
-3
79
257 MHz
MAX3K
-5
57
114 MHz
MAX7K
-5
57
114 MHz
Core performance in ALTERA® devices
Device
Transfer Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two
bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit,
which selects an active high or active low clock and has no significant effect on the transfer format.
The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats.
The clock phase and polarity should be identical for the master SPI device and the communicating
slave device. In some cases, the phase and polarity are changed between transfers to allow a
master device to communicate with peripheral slaves having different requirements. The flexibility
of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial
peripheral.
SC K C Y C L E#
SC K (C PO L=0)
SC K (C PO L=1)
M O SI
M ISO
SS
M SB
M SB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
1
2
3
4
5
6
7
8
SC K C YC L E#
SCK (CPO L=0)
SC K (C PO L=1)
M O SI
M ISO
SS
1
2
3
4
5
6
7
8
M SB
M SB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
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are trademarks of their respective owners.
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
