SYMBOL
clk
rst
datai(D:0)
cpha
cpol
sck
si
ss
datao(D:0)
address(A:0)
rd
we
so
ments. The flexibility of the SPI system on the
DSPIS allows direct interface to almost any
existing synchronous serial peripheral.
Shift register–
is a central element in the SPI
system. When an SPI transfer occurs, an 8-bit
character is shifted out on data pin while a
different 8-bit character is simultaneously
shifted in a second data pin. Another way to
view this transfer is that an 8-bit shift register
in the master and another 8-bit shift register in
the slave are connected as a circular 16-bit
shift register. When a transfer occurs, this
distributed shift register is shifted eight bit po-
sitions; thus, the characters in the master and
slave are effectively exchanged.
clk
rst
cpha
cpol
sck
PINS DESCRIPTION
PIN
clk
rst
datai(D:0)
cpha
cpol
sck
si
ss
datao(D:0)
addres(A:0)
rd
we
so
TYPE
input
input
input
input
input
input
input
input
output
output
output
output
output
DESCRIPTION
Global clock
Global reset
Data bus input
SCK clock phase
SCK clock polarity
SPI serial clock
SPI serial data input
Slave select
Data bus output
Address bus output
Read output
Write enable
Slave serial data output
SPI Clock Logic
so
MSB
Shift Reg.
LSB
si
datai
Data reg
.
Adr. reg
.
SPI
Controller
ss
datao
address
we
rd
Data Register
holds data read from passive
device and to be sent serially to the SPI Mas-
ter.
Address Register
holds address presented
on Address bus. it’s contents is incremented
every single data portion sent/received serially
through the SPI bus.
SPI Controller
- detects begin and end of SPI
transfer. Manages data exchange between
DSPIS and passive device controlled by
DSPIS, and increment Address Register
(SPAD) after any successful transfer.
BLOCK DIAGRAM
SPI Clock logic
controls phase and polarity of
the SCK clock line, and detects correct sam-
ple and shift edge for the Shift register. SPI
clock Logic allow user to select any of four
combinations of serial clock (SCK) phase and
polarity using two pins CPHA and CPOL. The
clock polarity is specified by the CPOL, which
selects an active high or active low clock and
has no significant effect on the transfer format.
The clock phase CPHA selects one of two
fundamentally different transfer formats. The
clock phase and polarity should be identical
for the master SPI device and the communi-
cating slave device. In some cases, the phase
and polarity are changed between transfers to
allow a master device to communicate with
peripheral slaves having different require-
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are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
