KEY FEATURES
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LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design
license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year
licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except
One Year
license where time of
use is limited to 12 months.
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SPI Slave
Slave operation
Automatic read and write operations
Automatic address incrementation after any
data portion transfer
Configurable address and data length.
Configurable SCK phase and polarity.
Supports speeds up ¼ of system clock
Simple interface allows easy connection to
passive devices, and SPI Master
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Fully synthesizable, static synchronous
design with no internal tri-states
DELIVERABLES
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Source code:
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VHDL Source Code or/and
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VERILOG Source Code or/and
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Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environ-
ment
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Active-HDL automatic simulation macros
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ModelSim automatic simulation macros
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Tests with reference responses
Technical documentation
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Installation notes
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HDL core specification
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Datasheet
Synthesis scripts
Example application
Technical support
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IP Core implementation support
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3 months maintenance
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Delivery the IP Core updates, minor
and major versions changes
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Delivery the documentation updates
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Phone & email support
Single Design license for
VHDL, Verilog source code called HDL
Source
Encrypted, or plain text EDIF called Netlist
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One Year license for
Encrypted Netlist only
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Unlimited Designs license for
HDL Source
Netlist
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Upgrade from
HDL Source to Netlist
Single Design to Unlimited Designs
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All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
