prgdatao[7:0]
prgdataz
prgrd
output Output data bus for Program Memory
output PRGDATA tri-state buffers control line
output Program Memory read
U N I T S S U M M A R Y
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module. Program fetch cycle length
can be programmed by user. This feature is
called Program Memory Wait States, and al-
lows core to work with different speed program
memories.
External Memory Interface – Contains mem-
ory access related registers such as Data
Pointer High (DPH0, DPH1), Data Pointer Low
(DPL0, DPL1), Data Page Pointer (DPP0,
DPP1), MOVX @Ri address register (MXAX)
and STRETCH registers. It performs the mem-
ory addressing and data transfers. Allows ap-
plications software to access up to 16 MB of
external data memory. The DPP0, DPP1 reg-
isters are used for segments swapping.
STRETCH register allows flexible timing man-
agement while accessing different speed sys-
tem devices by programming XRAMWR and
XRAMRD pulse width between 1 – 8 clock pe-
riods.
prgwr
output Program Memory write
xramdatao[7:0] output Data bus for External Data Memory
xramdataz output XDATA tri-state buffers control line
xramaddr[23:0] output External Data Memory address bus
xramrd
xramwr
docddatao
docdclk
pmm
output External Data Memory read
output External Data Memory write
output DoCD™ data output
output DoCD™ clock line
output Power management mode indicator
output Stop mode indicator
output Port 0 output
stop
port0o[7:0]
port1o[7:0]
port2o[7:0]
port3o[7:0]
rxd0o
output Port 1 output
output Port 2 output
output Port 3 output
output Serial receiver output 0
output Serial transmitter line 0
output Serial receiver output 1
output Serial transmitter line 1
output Master I2C clock output
output High speed Master I2C clock line
output Master I2C data output
output Slave I2C clock output
output Slave I2C data output
output SPI slave select lines
output SPI slave output
txd0
rxd1o
txd1
msclo
msclhs
msdao
msclo
msdao
sso[7:0]
so
mo
output SPI master output
scko
output SPI clock output
sckz
output SPI clock line tri-state buffer control
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
