○ Pulses generation
○ Digital signals generation
○ Gated timers
- Harward
Memory style
•
•
•
•
•
•
•
•
•
•
•
•
•
- von Neumann
- synchronous
- asynchronous
○ Sophisticated comparator
○ Pulse width modulation
○ Pulse width measuring
● Fixed-Point arithmetic coprocessor
○ Multiplication - 16bit * 16bit
○ Division - 32bit / 16bit
○ Division - 16bit / 16bit
○ Left and right shifting - 1 to 31 bits
○ Normalization
Program Memory type
Program Memory wait-
states
- used (0-7)
- unused
- used
Program Memory writes
- unused
- synchronous
- asynchronous
Internal Data Memory type
External Data Memory
wait-states
- used (0-7)
- unused
Second Data Pointer
(DPTR1)
- used
- unused
● Floating-Point arithmetic coprocessor IEEE-
754 standard single precision
- used
Data Pointers decrement
Data Pointers auto-switch
Interrupts
- unused
○ FADD, FSUB - addition, subtraction
○ FMUL, FDIV- multiplication, division
○ FSQRT- square root
- used
- unused
subroutines
-
○ FUCOM - compare
location
○ FCHS - change sign
- used
Timing access protection
Power Management Mode
Stop mode
- unused
○ FABS - absolute value
- used
● Floating-Point math coprocessor - IEEE-754
standard single precision real, word and
short integers
- unused
- used
- unused
○ FADD, FSUB- addition, subtraction
○ FMUL, FDIV- multiplication, division
○ FSQRT- square root
- used
• DoCD debug unit
- unused
○ FUCOM- compare
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
○ FCHS - change sign
○ FABS - absolute value
○ FSIN, FCOS- sine, cosine
○ FTAN, FATAN- tangent, arcs tangent
D E L I V E R A B L E S
♦
♦
♦
Source code:
C O N F I G U R A T I O N
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
The following parameters of the DR8051XP
core can be easy adjusted to requirements of
dedicated application and technology. Configu-
ration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
◊ Installation notes
◊ HDL core specification
◊ Datasheet
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
